[ CourseMega Com ] Udemy - UART Design and Simulation Using Verilog HDL Programming
File List
| File | Size |
|---|---|
| Get Bonus Downloads Here.url | 180 B |
| ~Get Your Files Here !/01 - Introduction/001 Preview.mp4 | 27.07 MB |
| ~Get Your Files Here !/01 - Introduction/001 Preview_en.vtt | 4.55 KB |
| ~Get Your Files Here !/01 - Introduction/002 Introduction to Serial Communication.mp4 | 6.21 MB |
| ~Get Your Files Here !/01 - Introduction/002 Introduction to Serial Communication_en.vtt | 1.07 KB |
| ~Get Your Files Here !/01 - Introduction/003 Limitations of parallel communication and Advantage of Serial communication.mp4 | 24.19 MB |
| ~Get Your Files Here !/01 - Introduction/003 Limitations of parallel communication and Advantage of Serial communication_en.vtt | 2.76 KB |
| ~Get Your Files Here !/01 - Introduction/004 Synchronous & Asynchronous Serial communication.mp4 | 5.82 MB |
| ~Get Your Files Here !/01 - Introduction/004 Synchronous & Asynchronous Serial communication_en.vtt | 970 B |
| ~Get Your Files Here !/02 - Introduction to UART/001 What is UART.mp4 | 6.91 MB |
| ~Get Your Files Here !/02 - Introduction to UART/001 What is UART_en.vtt | 1.36 KB |
| ~Get Your Files Here !/02 - Introduction to UART/002 Data format of UART.mp4 | 3.3 MB |
| ~Get Your Files Here !/02 - Introduction to UART/002 Data format of UART_en.vtt | 632 B |
| ~Get Your Files Here !/02 - Introduction to UART/003 Transmission & Reception operations in UART.mp4 | 29.82 MB |
| ~Get Your Files Here !/02 - Introduction to UART/003 Transmission & Reception operations in UART_en.vtt | 4.83 KB |
| ~Get Your Files Here !/02 - Introduction to UART/004 Block diagram for UART.mp4 | 10.37 MB |
| ~Get Your Files Here !/02 - Introduction to UART/004 Block diagram for UART_en.vtt | 2.78 KB |
| ~Get Your Files Here !/03 - Implementation of UART modules/001 Baud rate generator.mp4 | 11.73 MB |
| ~Get Your Files Here !/03 - Implementation of UART modules/001 Baud rate generator_en.vtt | 2.07 KB |
| ~Get Your Files Here !/03 - Implementation of UART modules/002 Verilog HDL for Baud rate generator.mp4 | 93.15 MB |
| ~Get Your Files Here !/03 - Implementation of UART modules/002 Verilog HDL for Baud rate generator_en.vtt | 10.26 KB |
| ~Get Your Files Here !/03 - Implementation of UART modules/003 FSM for UART Transmitter.mp4 | 6.72 MB |
| ~Get Your Files Here !/03 - Implementation of UART modules/003 FSM for UART Transmitter_en.vtt | 1.39 KB |
| ~Get Your Files Here !/03 - Implementation of UART modules/004 FSM for UART Receiver.mp4 | 5.54 MB |
| ~Get Your Files Here !/03 - Implementation of UART modules/004 FSM for UART Receiver_en.vtt | 1.22 KB |
| ~Get Your Files Here !/03 - Implementation of UART modules/005 Test bench environment.mp4 | 22.12 MB |
| ~Get Your Files Here !/03 - Implementation of UART modules/005 Test bench environment_en.vtt | 3.5 KB |
| ~Get Your Files Here !/03 - Implementation of UART modules/006 Hands on Verilog HDL for UART Transmitter with its Test Bench.mp4 | 531.38 MB |
| ~Get Your Files Here !/03 - Implementation of UART modules/006 Hands on Verilog HDL for UART Transmitter with its Test Bench_en.vtt | 45.57 KB |
| ~Get Your Files Here !/03 - Implementation of UART modules/007 Hands on Verilog HDL for UART Receiver with its Test Bench.mp4 | 326.25 MB |
| ~Get Your Files Here !/03 - Implementation of UART modules/007 Hands on Verilog HDL for UART Receiver with its Test Bench_en.vtt | 28.21 KB |
| ~Get Your Files Here !/03 - Implementation of UART modules/008 Hands on Added Logic for sample ticks in Verilog HDL for UART Receiver with TB.mp4 | 251.42 MB |
| ~Get Your Files Here !/03 - Implementation of UART modules/008 Hands on Added Logic for sample ticks in Verilog HDL for UART Receiver with TB_en.vtt | 25.9 KB |
| ~Get Your Files Here !/Bonus Resources.txt | 386 B |
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